An ASIC for data over SONET/SDH mapping and path protection switching

This paper presents an ASIC for mapping data over SONET/SDH. The chip is designed to provide mapping from data sources such as Ethernet and IP frames into SONET/SDH. It supports data encapsulating using high level data link control (HDLC), X.86 (Ethernet over LAPS), generic framing procedure, and mapping the services into SONET/SDH signals using virtual concatenation. It also supports the unidirectional path switch ring (UPSR) applications. The power of the chip can be greatly reduced by turning unused paths to sleeping mode with control bits and separating the low frequency parts with different clock domain. The chip is fabricated in TSMC 130 nm process, and has about 8 M gates.