Title :
Tree multipliers with modified Booth algorithm based on adiabatic CPL
Author :
Liu, Binbin ; Hu, Jianping
Author_Institution :
Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo, China
Abstract :
This paper describes an adiabatic tree multiplier based on modified booth algorithm, which operates on four-phase power clocks. It is composed of booth encoder, partial product generators followed by booth encoding, a complementary decoder that is required by the partial product generator, Wallace trees with 4-2 compressors, and a final carry-lookahead adder. All circuits are realized by CPAL (complementary pass-transistor adiabatic logic) circuits with TSMC 0.18 ¿m CMOS process technology. Compared with its CMOS counterpart based on conventional logic circuits, the four-phase adiabatic multiplier attains energy savings of 86.6% at 50 MHz and 72.8% at 300 MHz, respectively.
Keywords :
CMOS digital integrated circuits; clocks; logic circuits; multiplying circuits; TSMC CMOS process technology; Wallace trees; adiabatic CPL; adiabatic tree multiplier; booth encoder; complementary decoder; complementary pass-transistor adiabatic logic circuits; compressors; final carry-lookahead adder; four-phase adiabatic multiplier; four-phase power clocks; frequency 300 MHz; frequency 50 MHz; modified booth algorithm; partial product generators; size 0.18 mum; Adders; CMOS logic circuits; CMOS technology; Clocks; Compressors; Decoding; Encoding; Logic arrays; Logic circuits; Signal processing algorithms; adibatic logic; modified booth encoder; tree multiplier;
Conference_Titel :
Integrated Circuits, ISIC '09. Proceedings of the 2009 12th International Symposium on
Conference_Location :
Singapore
Print_ISBN :
978-9-8108-2468-6
