Tree multipliers with modified Booth algorithm based on adiabatic CPL

This paper describes an adiabatic tree multiplier based on modified booth algorithm, which operates on four-phase power clocks. It is composed of booth encoder, partial product generators followed by booth encoding, a complementary decoder that is required by the partial product generator, Wallace trees with 4-2 compressors, and a final carry-lookahead adder. All circuits are realized by CPAL (complementary pass-transistor adiabatic logic) circuits with TSMC 0.18 ¿m CMOS process technology. Compared with its CMOS counterpart based on conventional logic circuits, the four-phase adiabatic multiplier attains energy savings of 86.6% at 50 MHz and 72.8% at 300 MHz, respectively.