A low-complexity power-efficient synchronization scheme for wireless communication system

This paper presents a low-cost power-efficient scheme and circuitry for synchronizing in a wireless communication system. By reusing the over-sampling circuitry for frame-synchronization of the wireless system, we can achieve bit synchronization without using PLL CDR Architecture. The over-sampling circuitry is turned-on periodically to achieve low-power. The scheme has been used and verified in a low-power baseband IC. The only overhead is just some logic gates to add-on for the system. The chip is fabricated using Chartered 0.18 ¿m CMOS process and total baseband area is just 300 ¿m × 300 ¿m. The whole chip area with analogue modulator/demodulator is only 2000 ¿m × 2000 ¿m.