Title :
Design and performance evaluation of a low-power data-line SRAM sense amplifier
Author :
Fu, Haitao ; Yeo, Kiat-Seng ; Do, Anh-Tuan ; Kong, Zhi-Hui
Author_Institution :
Dept. of Mater. Sci. & Eng., Massachusetts Inst. of Technol., Cambridge, MA, USA
Abstract :
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. The heavy bit-and data-line capacitances are the major road blocks to its performance. A high-performance SRAM is proposed using a 1.8 V/0.18 ¿m CMOS standard process from Chartered Semiconductor Manufacturing Ltd (CHRT). It incorporates a discharging mechanism that helps eliminating the waiting time during the read operation, hence offering a faster sensing speed and lower power consumption. Our post-layout simulation results have shown that it improves the sensing speed and power consumption by 51.4%, and 62.47%, respectively when compared with the best published design. The total power-delay-product (PDP) is 81.79% better. Furthermore, it can operate at a supply voltage as low as 0.8 V with a high stability to the bit-line capacitances variation and mismatch.
Keywords :
CMOS integrated circuits; SRAM chips; amplifiers; cache storage; logic design; low-power electronics; system-on-chip; CHRT; CMOS standard process; Chartered Semiconductor Manufacturing Ltd; bit-line capacitances variation; data-line capacitances; discharging mechanism; electronic industry; low-power data-line SRAM sense amplifier evaluation; lower power consumption; post-layout simulation; size 0.18 mum; system-on-chip; total power-delay-product; voltage 1.8 V; CMOS process; Capacitance; Electronics industry; Energy consumption; Low voltage; Manufacturing processes; Random access memory; Roads; Semiconductor device manufacture; System-on-a-chip;
Conference_Titel :
Integrated Circuits, ISIC '09. Proceedings of the 2009 12th International Symposium on
Conference_Location :
Singapore
Print_ISBN :
978-9-8108-2468-6
