DocumentCode :
511799
Title :
A new flip-flop based on multiple leakage reduction techniques
Author :
Zhang, Weiqiang ; Li, Linfeng ; Hu, Jianping
Author_Institution :
Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo, China
fYear :
2009
fDate :
14-16 Dec. 2009
Firstpage :
73
Lastpage :
76
Abstract :
In present CMOS circuits, the scaling of transistor sizes has resulted in dramatic increase of leakage currents. The sub-threshold and gate leakages have now become a major contributor to both leakage dissipations and total power consumptions. This paper proposes a new flip-flop, which uses P-type CMOS technique, power-gating and dual threshold technique to reduce both sub-threshold and gate leakage circuits. Simulation results show that the proposed MLRT (multiple leakage reduction technique) flip-flop saves 60-70% leakage power dissipations and 40-50% total power consumptions compared with the single-threshold transmission gate one.
Keywords :
CMOS digital integrated circuits; flip-flops; leakage currents; CMOS circuits; P-type CMOS technique; dual threshold technique; flip-flop; gate leakage circuits; leakage currents; leakage power dissipations; multiple leakage reduction techniques; power gating; single-threshold transmission gate; total power consumptions; CMOS technology; Circuits; Delay; Energy consumption; Feedback; Feeds; Flip-flops; Gate leakage; Inverters; Leakage current; P-type CMOS technique; dual threshold technique; leakage reduction; power-gating technique;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Integrated Circuits, ISIC '09. Proceedings of the 2009 12th International Symposium on
Conference_Location :
Singapore
Print_ISBN :
978-9-8108-2468-6
Type :
conf
Filename :
5403866
Link To Document :
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