A 1.8 V to 3.3 V level-converting flip-flop design for multiple power supply systems

The voltage islands scheme using multiple supply voltages (MSV) has been widely used in system-on-chip (SoC) designs to reduce the unnecessary power dissipation in non-critical function blocks. In these SoC designs, the circuit blocks with the same voltage level are clustered into a single voltage island to reduce the cost of voltage supply network and the power consumption. However, a voltage level converter is required to stitch different voltage islands when the normal scan mode is activated. Besides carrying out the scan testing function, the level converter should be able to overcome the gate-oxide overstress problem given more than two supply voltages and backward compatibility. In this study, a 1.8 V to 3.3 V level converting flip-flop (LCFF) implemented using 0.18 ¿m CMOS technology is proposed. By utilizing the voltage keeper technique, the power consumption and the power delay product (PDP) can be successfully reduced without any leakage current path.