High-speed low-complexity Folded Degree-Computationless Modified Euclidean algorithm architecture for RS decoders

This paper presents a novel high-speed low-complexity folded degree-computationless modified Euclidean (fDCME) algorithm and its architecture for Reed-Solomon (RS) decoders. The proposed scheme uses the fully folded systolic architecture in which two array of processing element computes both the error locator and the error value polynomials. The pipelined folded structure enables the novel low-complexity pipelined fDCME architecture to reduce the number of processing elements. A high-speed low-complexity RS decoder based on the fDCME algorithm has been designed and implemented with 90 nm CMOS standard cell technology in a supply voltage of 1.2 V. The proposed RS decoder operates at a clock frequency of 660 MHz and has a throughput of 5.3 Gb/s. The proposed architecture requires approximately 70% fewer gate counts and a simpler control logic than previous architectures based on the popular modified Euclidean algorithm.