Title :
A novel 1.2 Gbps LVDS receiver for multi-channel applications
Author :
Lin, Yingyan ; Kang, Wenjing ; Chen, Xiaofei ; Zhang, Jing ; Zou, Xuecheng
Author_Institution :
Dept. of Electron. Sci. & Technol., Huazhong Univ. of Sci. & Technol., Wuhan, China
Abstract :
This paper presents a new LVDS clock and data recovery (CDR) circuit for use in multi-channel applications. Combining a deskewing module together with a novel sampling clock generator achieves immunity to skew effects between channels as well as collective jitter due to process, power supply, and temperature variations. Besides, by dynamically tracking eye edges and introducing different strategies for eye edges occurring at different regions, the proposed circuit can generate sampling clocks aligned to middle of the data eye, and hence offers maximum amount of timing margin and improved jitter tolerance. The proposed CDR circuit has been designed in a TSMC 90 nm CMOS process. Simulation results demonstrate that when skew plus jitter jumping around 0.3 UI and 0 UI points for the input 211-1 pseudorandom bit sequences (PRBS), the circuit can recover correctly data at frequency from 175 MHz to 1.2 GHz.
Keywords :
CMOS digital integrated circuits; clock and data recovery circuits; clocks; jitter; random sequences; CDR circuit; LVDS clock and data recovery circuit; LVDS receiver; TSMC CMOS process; bit rate 1.2 Gbit/s; collective jitter; deskewing module; frequency 175 MHz to 1.2 GHz; improved jitter tolerance; power supply; pseudorandom bit sequences; sampling clock generator; size 90 nm; skew effects; temperature variations; timing margin; CMOS process; Circuit simulation; Clocks; Crosstalk; Frequency; Power generation; Power supplies; Sampling methods; Temperature; Timing jitter; clock and data recovery circuit(CDR); jitter; sampling clock generator; skew;
Conference_Titel :
Integrated Circuits, ISIC '09. Proceedings of the 2009 12th International Symposium on
Conference_Location :
Singapore
Print_ISBN :
978-9-8108-2468-6
