DocumentCode
511828
Title
A high-performance multibit-flipping algorithm for LDPC decoding
Author
Hung, Jui-Hui ; Chen, Sau-Gee
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
2009
fDate
14-16 Dec. 2009
Firstpage
151
Lastpage
154
Abstract
For LDPC decoding, bit-flipping (BF) algorithms are much simpler than the min-sum algorithms (MSA). However, BF algorithms have the disadvantages of poorer performances and higher iteration counts than MSA. This paper introduces the concepts of low correlation search and culprit vote to further improve the efficiency of the existing BF algorithms. High decoding performances and low iteration number are achieved by flipping those bits with low correlation as much as possible and introducing an additional syndrome vote procedure. As a result, the proposed algorithm can achieve significant decoding performance which is very close to the min-sum algorithm (MSA) but with much lower computation complexity.
Keywords
communication complexity; decoding; parity check codes; LDPC decoding; additional syndrome vote procedure; computation complexity; high decoding performances; high-performance multibit-flipping algorithm; iteration counts; low correlation search; min-sum algorithms; Algorithm design and analysis; Bipartite graph; Block codes; Digital video broadcasting; Hardware; Iterative decoding; Parity check codes; Sparse matrices; Sum product algorithm; Voting; LDPC codes; bit-flipping algorithm; channel coding;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuits, ISIC '09. Proceedings of the 2009 12th International Symposium on
Conference_Location
Singapore
Print_ISBN
978-9-8108-2468-6
Type
conf
Filename
5403898
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