A low dropout linear regulator with high power supply rejection

Author

Jhuang, Huei-Sheng ; Wang, Jia-Hui ; Zeng, Zi-Yu ; Tsai, Chien-Hung

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

2009

fDate

14-16 Dec. 2009

Firstpage

41

Lastpage

44

Abstract

Combining the supply ripple subtraction and high-pass filtering can improve the power supply rejection (PSR) over wideband frequency of low dropout regulator (LDO). The proposed LDO is fabricated by TSMC 0.35 Â¿m 2-poly 4-metal CMOS process. The simulation results at maximum load current of 100 mA, show that PSR at 10 k, 100 k and 1 M are -72 dB, -75 dB and -46 dB, respectively. Therefore, it´s well suited for switching pre-regulator and SoC applications. The active area of this LDO is 300Ã—360 Â¿m².

Keywords

CMOS integrated circuits; controllers; power supplies to apparatus; system-on-chip; voltage regulators; 2-poly 4-metal CMOS process; SoC application; current 100 mA; high power supply rejection; load current; low dropout linear regulator; noise figure -72 dB to -46 dB; pre-regulator application; size 0.35 mum; Clocks; Crosstalk; Filtering; Frequency; Power supplies; Regulators; Switched-mode power supply; Voltage; Voltage-controlled oscillators; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits, ISIC '09. Proceedings of the 2009 12th International Symposium on

Conference_Location

Singapore

Print_ISBN

978-9-8108-2468-6

Type

conf

Filename

5403904