Area-saving technique for low-error redundant binary fixed-width multiplier implementation

A recently proposed architecture of redundant binary fixed-width multiplier was shown to outperform several normal binary fixed-width multipliers in terms of accuracy. However, its merit due to the carry-free addition property of the binary signed digit (BSD) partial products has been offset by the high area overhead of the redundant binary full adder tree. To achieve low-error fixed-width multiplication with smaller silicon area, we propose a hybrid structure which makes use of dual polarity high order column compressors and (3:2) counters to parallelly reduce the positive and negative BSD partial products. Our proposed technique has led to a fixed-width multiplier architecture with the same accuracy and up to 42% area saving for 10×10-bit multiplication over the conventional redundant binary fixed-width multiplier architecture in 0.18 ¿m CMOS standard cell implementation under the same timing constraint.