Impact of process variation on timing characteristics of MTCMOS flip-flops for low-power mobile multimedia applications

In mobile multimedia applications, low power is a very important requirement for hardware systems. Reducing the standby power to a negligible level, multi-threshold CMOS (MTCMOS) has been accepted as one of the most effective circuit techniques for low power design of the mobile equipments. However, the aggressive technology scaling has increased process variation, which in turn has caused significant changes in system performance and behavior of the designed circuits. Thus, process variation affects not only the performance of the MTCMOS circuits but also the yield of MTCMOS SoCs today. Therefore, the investigation of the effect of process variation becomes more important than ever. This paper investigates representative MTCMOS flip-flop architectures in the timing sensitivity to process variation. To consider the impacts of process variation accurately, Monte-Carlo simulation was used and the results were compared in timing variability and yield. Also, this paper shows which process parameter gives the largest impact on timing variations of the MTCMOS flip-flops. In addition, the differences of timing variation characteristics under different technology nodes are presented. Finally, this paper investigates the usefulness of the conventional corner-based analysis on the MTCMOS flip-flops under the ultra deep submicron process technology today.