Characterization and implementation of nonlinear logic cell models for analog circuit simulation

During back-end verification of digital circuits, analog circuit simulation is an indispensable, but time consuming, process. To reduce simulation time, current source models (CSMs) have been proposed to replace transistor netlists of logic cells. In this paper, physically motivated requirements for accurate CSMs are derived. By employing the topological information of the netlist, very short characterization times and high accuracy are achieved. Implemented as compiled models in a standard SPICE simulator, CSMs reduce simulation times by two orders of magnitude.