IP-XACT components with abstract time characterization

Large system-on-chips are built by assembly of components modeled at different representation levels (TLM, RTL). The IP-XACT standard focuses on structure, type and memory information and ignores behavior and time issues. The UML profile for MARTE and its companion language CCSL provide advanced time modeling capabilities. By combining UML MARTE and IP-XACT, we introduce a more abstract timed representation level allowing the description of IP-XACT designs with UML-based environments. This paper discusses the use of MARTE to annotate IP-XACT specifications with time requirements. These time requirements are first used in simulation to generate waveforms. Then, actual implementations are considered and adequate observers are generated to validate these implementations with respect to the MARTE specification. The proposal is illustrated on the Leon2 architecture and specifically on its AHB to APB bridge.