A SystemC superset for high-level synthesis

Today´s system-on-a-chip (SoC) designs are becoming more and more complex. This creates demand for system level computer-aided-design (CAD) tools that allow early hardware and software co-development, hardware and software performance evaluation and fast system-level modeling. The latest achievements in this area are mostly due to wide SystemC adoption and the recent introduction of the TLM 2.0 standard. The complexity of today´s SoC designs makes high-level synthesis (HLS) an important part of modern design flows. In this paper, we analyze two basic approaches to HLS user input that exist today sequential ANSI C/C++ and SystemC synthesizable subset. Based upon the results of our analysis, we propose a new concept SystemC synthesizable superset a solution that combines advantages of both approaches (ANSI C/C++ and SystemC), but does not inherit their disadvantages. Our HLS-oriented concept features a predefined library of HLS modules, user threads with implicit timing specification and a set of TLM 2.0 compatible interfaces. In addition, our HLS objects allow for various levels of simulation abstraction (or timing accuracy), such as cycle-accurate at transaction boundaries (CATB), approximately-timed and loosely-timed modeling. Simulation abstraction levels can be switched without the need to rewrite the user system specification that determines high flexibility level of our solution. In conclusion, we demonstrate a simple synthesizable video system and compare the simulation speeds at different abstraction levels.