DocumentCode
512623
Title
On-line error detection and testing of AES
Author
Patil, Jayashri
Author_Institution
Int. Inst. of Inf. Technol., Pune, India
fYear
2009
fDate
14-16 Dec. 2009
Firstpage
1
Lastpage
4
Abstract
The paper proposes low cost on-line error detection architecture for advanced encryption standard algorithm. The implementation is optimized for FPGA based embedded applications since it is tuned to specific FPGA logic resources. In order to provide more reliable operation and reduce the possibility of suffering from fault-based side channel attacks, the on-line error detection based on parity codes is developed.
Keywords
cryptography; embedded systems; field programmable gate arrays; AES testing; FPGA logic resources; advanced encryption standard algorithm; embedded application; low cost online error detection architecture; parity code; Computational Intelligence Society; Cryptography; Field programmable gate arrays; Hardware; Read only memory; Read-write memory; Shift registers; Strontium; Table lookup; Testing; AES; BIST; FPGA; round key;
fLanguage
English
Publisher
ieee
Conference_Titel
Computers and Devices for Communication, 2009. CODEC 2009. 4th International Conference on
Conference_Location
Kolkata
Print_ISBN
978-1-4244-5073-2
Type
conf
Filename
5407187
Link To Document