High-speed ASIC implementation of AES supporting 128/192/256 bits

Author

Yin, Huang ; Debiao, He ; Yong, Kang ; Xiande, Fei

Author_Institution

Sch. of Math. & Stat., Wuhan Univ., Wuhan, China

Volume

1

fYear

2009

fDate

5-6 Dec. 2009

Firstpage

95

Lastpage

98

Abstract

This paper presented an efficient ASIC implementation of the Advanced Encryption Standard (AES) algorithm encryption/decryption, with key expansion capability. A new way of implementing MixColumns and InvMixColumns transformations using shared logic resources was also explored. The implementation supports 128bits, 192 bits and 256 bits input key. In the hardware architecture, the arithmetic operations in finite field GF(2⁸) can be designed efficiently with combinational logic, and takes advantages of table lookup method.

Keywords

Galois fields; application specific integrated circuits; cryptography; formal logic; AES; InvMixColumns transformations; MixColumns transformations; advanced encryption standard algorithm; finite field arithmetic; high-speed ASIC implementation; shared logic resources; table lookup method; Application specific integrated circuits; Arithmetic; Cryptography; Galois fields; Hardware; Helium; Military standards; NIST; Table lookup; Testing; Advanced Encryption Standard (AES); Application Specific Integrated Circuit (ASIC); Finite Field Arithmetic; Inversion;

fLanguage

English

Publisher

ieee

Conference_Titel

Test and Measurement, 2009. ICTM '09. International Conference on

Conference_Location

Hong Kong

Print_ISBN

978-1-4244-4699-5

Type

conf

DOI

10.1109/ICTM.2009.5412884

Filename

5412884