A theoretical study of error mechanisms in switched-current circuits

Author

Abbes, Karim ; Masmoudi, Mohamed

Author_Institution

Electron., Microtechnol. & Commun. (EMC) Res. Group, Nat. Eng. Sch. of Sfax, Sfax, Tunisia

fYear

2009

fDate

6-8 Nov. 2009

Firstpage

1

Lastpage

4

Abstract

This paper describes a theoretical study of the main errors in switched-current (SI) cells, such as conductance ratio error, settling time error and charge injection error, and their influence on the output/input transfert characteristic. First, our interest is focused on the study each error mechanism and its effect on the SI memory cell. After that, we studied the influence of their cumulative effect. Finally, we detailed the effect of cumulative error on the integrator level. The most significant non-idealities of SI cell are identified and their cumulative effect on SI cell and SI integrator transfert characteristic are analytically demonstrated.

Keywords

charge injection; integrated circuit testing; integrated memory circuits; integrating circuits; switched current circuits; charge injection error; conductance ratio error; cumulative error; error mechanisms; settling time error; switched-current cells; switched-current circuits; Analog-digital conversion; Circuits and systems; Clocks; Communication switching; Data conversion; Delay; Electromagnetic compatibility; Signal processing; Switching circuits; Voltage; Δ - Σ Analog to digital converters; Switched-current circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Circuits and Systems (SCS), 2009 3rd International Conference on

Conference_Location

Medenine

Print_ISBN

978-1-4244-4397-0

Electronic_ISBN

978-1-4244-4398-7

Type

conf

DOI

10.1109/ICSCS.2009.5414152

Filename

5414152