Study of the correlation between the simulated and the measured results for signal integrity parameters

As the clock frequencies for digital circuits rise and the edge rates increase there is an increased emphasis on the PCB design part to meet the timing margins. The interconnect design which was hitherto ignored has now become an important link which can make or break the system. By optimum design it is possible to achieve better results and reliable operation throughout the lifetime of the system. In this regard simulation of the design takes a center stage for ensuring optimum results in design. With the aid of simulation it is possible to obtain results for the effect of the variation of the different parameters on the end product. But the use of simulation tools does not suffice to ensure a reliable design. The simulation tools are based on mathematical algorithms which have a certain level of accuracy. Moreover IBIS models of the devices have a limit to their accuracy that introduces a limit to the accuracy of the results. The work undertaken in this paper aims to correlate the quantum of mismatch between the simulated and the measured results.