Analysis of Parasitic Effects in Advanced Isolation Schemes for Deep Submicron CMOS Technologies

The evolution of the active area/isolation transition has resulted in a modification of the isolation induced parasitic effects on the device. Using experimental results and simulations, we have analysed the corner parasitic transistor behaviour induced by an abrupt transition. We show that some technological parameters linked to the isolation process must be perfectly controlled for a good integration of future isolation technologies, especially for the shallow trench isolation (STI).