Localized Lifetime Control in Bipolar Silicon Devices

A method to control carrier lifetime in silicon locally and efficiently is presented. It is based on the formation of void layers by high dose He implants and annealing. Layers thinner than 100 nm with a lateral extent limited only by the implantation mask can be obtained. They introduce two well defined mid gap trap levels in silicon for holes and electrons. These characteristics make voids ideal for lifetime control. Two applications are suggested: the reduction of parasitic transistor gain and the carrier recombination control in IGBTs.