Title :
MOSFET Matching in a Deep Submicron Technology
Author :
Buisson, Olivier Roux dit ; Morin, Gérard
Author_Institution :
SGS-THOMSON Microelectronics, 850 Rue Jean Monnet - BP16, 38921 CROLLES CEDEX, FRANCE.
Abstract :
MOSFET matching is a key issue for specific mixed analog/digital CMOS designs. In this paper, this analog property is evaluated in an industrial deep submicron technology. Matching of CMOS 0.35 ¿m devices is evaluated versus gate area (307.2 ¿m2 down to 0.42 ¿m2), biases and spacing distance between devices. Lowest threshold voltage matching parameters are presented, as compared to the state-of-the-art of CMOS technologies. In conclusion, MOSFET matching is improved with scaling, as compared to previous generations.
Keywords :
CMOS process; CMOS technology; Current measurement; MOSFET circuits; Measurement standards; Performance evaluation; Size measurement; Standards development; Threshold voltage; Transconductance;
Conference_Titel :
Solid State Device Research Conference, 1996. ESSDERC '96. Proceedings of the 26th European
Conference_Location :
Bologna, Italy
