Impact OF 0.25 μm NMOS Drain Engineering on Performance and Reliability

We have discussed in terms of drain current level, DIBL control and long term reliability three kinds of NMOS drain engineering (LDD, LATID and abrupt S/D ) implemented on a 0.25 μm CMOS technology in order to define the proper design/process device. First, main experimental results and device lifetime of these various drain structures have been compared. Then analysis of aging measurements as a function of substrate current, gate length and stress bias has been carried out. Different modes of degradation according to source/drain structure have been confirmed by 2D process and device simulations. A 10 years of device lifetime will be ensured for the nominal 0.25 μm gate length with a supply voltage of respectively 2.5 Volt for LDD and 2.0 Volt for abrupt source/drain.