Shallow Trench Isolation for Sub 1/4 Micron CMOS Technologies

This paper presents a Shallow Trench Isolation process (STI) for sub 1/4¿m CMOS technologies. The features of this STI technology are vertical trench sidewalls, a low field oxide temperature annealing, a counter-mask oxide etching step and a complete CMP step with a stop on nitride. The field oxide thickness uniformity is about 6% within a 200mm wafer. N+/N+ isolation is higher than 7.5V down to a 0.3¿m trench width. The inverse narrow channel effect is reduced to 110mV (NMOS) for channel width down to 0.25¿m. The high scalability of this process makes it suitable for 0.18¿m CMOS technologies and below.