Analysis of S/D Engineering through Short Channel Effect and Hot Carrier Injection behavior in a 0.35μm CMOS Technology

The evolution of the NMOS transistor Source/Drain engineering of a 0.35μm CMOS Technology is presented through the analysis of both Short Channel Effect (SCE) and Hot-Carrier Injection (HCI) behavior for various S/D architectures. Experimental and process/device simulation results provide a helpful understanding of the physical phenomena involved in the SCE and HCI. A trade-off between SCE and HCI is proposed.