DocumentCode :
513855
Title :
A 0.2 μm Emitter Bipolar Technology for Low Cost and High Performance Mixed Analog/Digital Applications
Author :
Miwa, Hiroyuki ; Ammo, Hiroaki ; Kato, Katsuyuki ; Ejiri, Hirokazu ; Kanematsu, Shigeru ; Mori, Hideki ; Gomi, Takayuki
Author_Institution :
Bipolar/CCD LSI Division, Semiconductor Company, SONY Corporation, 4-14-1, Asahi-cho, Atsugi-shi, Kanagawa-ken, 243 Japan
fYear :
1996
fDate :
9-11 Sept. 1996
Firstpage :
429
Lastpage :
432
Abstract :
A 0.2 μ m emitter bipolar technology with improved LOCOS isolation for low cost and high performance mixed analog/digital applications is presented. The technology features high speed transistors (Tpdmin=21ps, fTmax=30GHz), high ß and high emitter-base breakdown voltage transistors (β=700, BVebo=10V), low power IIL (Tpd*Pd=9fJ/gate), and triple layers of metal. Total process steps are reduced to 80% by means of improved LOCOSprocess instead of deep trench isolation, which is 22% less than our 0.8 μ m BiCMOS process steps. An HDD R/W Amp. IC, which needs BVebo of more than 4V, was realized using high β and high BVebo transistor. A 2.5GHz 2R IC was also realized, and the high-speed transistor performance was confirmed.
Keywords :
Analog integrated circuits; BiCMOS integrated circuits; Bipolar transistor circuits; Boron; CMOS technology; Cost function; Ion implantation; Isolation technology; Silicon; Stress;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid State Device Research Conference, 1996. ESSDERC '96. Proceedings of the 26th European
Conference_Location :
Bologna, Italy
Print_ISBN :
286332196X
Type :
conf
Filename :
5436212
Link To Document :
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