DocumentCode
513868
Title
Advanced Ti Salicide Process for Sub-0.2 μm CMOS
Author
Rostoll, M-L. ; Maury, D. ; Regolini, J-L. ; Haond, M. ; Delpech, P. ; Gayet, P. ; LeContellec, M.
Author_Institution
France Telecom CNET, BP98, 38243 Meylan Cedex, FRANCE
fYear
1996
fDate
9-11 Sept. 1996
Firstpage
93
Lastpage
96
Abstract
Because of the reduction of gate length and junction depth, we confirm that conventional TiSi2 formed by a 2-step RTA on sputtered Ti cannot be used for sub-0.35 μm. We have investigated new techniques using selective Si-epitaxy before sputtering Ti, and a more advanced technique that makes use of direct selective TiSi2 CVD deposition on gate and S/D. We show that these techniques provide solutions for silicidation of sub-0.2 μm CMOS devices.
Keywords
CMOS process; CMOS technology; Electric resistance; Implants; MOSFETs; Microelectronics; Silicidation; Sputter etching; Sputtering; Telecommunications;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1996. ESSDERC '96. Proceedings of the 26th European
Conference_Location
Bologna, Italy
Print_ISBN
286332196X
Type
conf
Filename
5436226
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