DocumentCode
513896
Title
Impact ionization effects in silicon vertical JFET´s
Author
Chantre, A. ; Granier, A. ; Degors, N. ; Nouailhat, A.
Author_Institution
France Telecom, CNET/CNS, Chemin du Vieux Chêne, B.P.98, F-38243 Meylan Cedex, France
fYear
1991
fDate
16-19 Sept. 1991
Firstpage
39
Lastpage
42
Abstract
This paper reports the observation and analysis of excess gate and substrate currents in advanced self-aligned vertical Si junction field-effect transistors (JFET´s). These currents are proposed to result from impact ionization effects, causing generation of minority holes in the channel and photo-generation of minority electrons in the substrate.
Keywords
Bipolar transistors; Charge carrier processes; FETs; Fabrication; Impact ionization; Microelectronics; Silicon; Substrates; Telecommunications; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1991. ESSDERC '91. 21st European
Conference_Location
Montreux, Switzerland
Print_ISBN
0444890661
Type
conf
Filename
5436257
Link To Document