Title :
Stacked capacitor cell technology for 16M DRAM using double self-aligned contacts
Author :
Fukuumoto, M. ; Naito, Y. ; Matsuyama, K. ; Ogawa, H. ; Matsuoka, K. ; Hori, T. ; Sakai, I. ; Nakao, I. ; Kotani, H. ; Iwasaki, H. ; Inoue, M.
Author_Institution :
Semiconductor Research Center, Matsushita Electric Ind. Co., Ltd., Moriguchi, Osaka, Japan
Abstract :
This paper describes key technology of a small sized stacked capacitor-cell for 16MDRAM. The main feature of the technology is unique and highly productive double self-aligned contact process for bit line and for storage node, whichl is immune against process fluctuations. The cell made by this process showed desirable characteristics for DRAM operation.
Keywords :
Boron; Breakdown voltage; Capacitors; Doping profiles; Geometry; Numerical analysis; Numerical simulation; Random access memory; Shape; Silicon;
Conference_Titel :
Solid State Device Research Conference, 1990. ESSDERC '90. 20th European
Conference_Location :
Nottingham, England
