Title :
A 10 GHz High Performance BICMOS Technology for Mixed CMOS/ECL ICs
Author :
Hoffmann, B. ; Klose, H. ; Meister, T. ; Kerner, I. ; Schreiter, R.
Author_Institution :
Siemens AG, Corporate Research, Otto-Hahn-Ring 6, 8000 Munich 83, FRG
Abstract :
A 12 ¿m BICMOS process is presented for the realization of high complexity CMOS-circuits together with high performance bipolar transistors on the same chip. n+-/p-buried layers, a p-well CMOS-process and a double - polysilicon selfaligned bipolar process are the main technology features. A cut - off frequency of 10 GHz as well as a CML gat delay time of 65 ps are the results obtained with this process.
Keywords :
BiCMOS integrated circuits; Bipolar transistors; CMOS process; CMOS technology; Delay effects; Flowcharts; Frequency; MOS devices; Modems; Protection;
Conference_Titel :
Solid State Device Research Conference, 1989. ESSDERC '89. 19th European
Conference_Location :
Berlin, Germany
