A New Analytical Model of CMOS Latch-up

Classical analytical models of CMOS latch-up assume that the latch-up phenomenon is the result of the interaction of two or more bipolar transistors. With such a model, sustaining of latch-up can be only explained by a sufficiently high value for the product of bipolar gains (classically ßn·ßp¿1 or ßn·ßp¿ f (Iddmax) [1]). Such an explanation fails with the reduction of gain at high injection current levels [2]. We can also ask, whether we can even speak of bipolar transistors when the base-collector junctions have disappeared. This effect can be observed in figure 1[3]. Our model of latch-up includes a novel, four terminal, bipolar transistor model. With it we can explain the sustaining of latch-up at high injection levels, voltage drops through the base can be accounted for, and the disappearance of the base-collector junction can be represented. Our model is compared with experimental results, and good correlation was seen between measured and simulated values of holding voltage.