DocumentCode
514046
Title
A Self-aligned Gate Definition Process with Submicron Gaps
Author
Warmerdam, L.F.P. ; Aarnink, A.A.I. ; Holleman, J. ; Wallinga, H.
Author_Institution
University of Twente, IC Technology and Electronics Department, P.O. Box 217, 7500 AF Enschede, Netherlands
fYear
1989
fDate
11-14 Sept. 1989
Firstpage
37
Lastpage
40
Abstract
A self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 ¿m and smaller are fabricated. The spacing is realized by an edge-etch technique, combined with anisotropic plasma etching of the single poly-silicon layer. Straight gaps with minor width variation are fabricated. Minority carrier life-time and breakdown voltage are not affected.
Keywords
Anisotropic magnetoresistance; CMOS process; Etching; Isolation technology; Lithography; Performance evaluation; Plasma applications; Plasma simulation; Potential well; Silicon compounds;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1989. ESSDERC '89. 19th European
Conference_Location
Berlin, Germany
Print_ISBN
0387510001
Type
conf
Filename
5436674
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