CMOS Technology with Self-Aligned Contacts and Self-Aligned Silicide

Simple process modifications are proposed to notably increase the packing density of a given CMOS technology. These include the self-alignment of source-drain contacts together with the self-aligned silicidation of the diffusion regions and the polysilicon lines. The required gate sealing makes use of the sidewall spacer technique. The proposed changes have been incorporated into our conventional CMOS technology. The use of self-aligned contacts and self-aligned silicide allows to reduce the circuit surface of a C²-MOS latch by a factor of 2.4 and the gate delay of a ring oscillator by a factor of 1.6.