Title :
Shallow Junction Contacts for Latch Up Resistance in CMOS
Author :
Ruddell, F ; Ling, E. ; Armstrong, B.M. ; Gamble, H.S. ; Raza, S.H.
Author_Institution :
Department of Electrical and Electronic Engineering, The Queen´´s University of Belfast, Ashby Building, Belfast BT9 5AH. N. Ireland
Abstract :
An optimum TiSi2 thickness of 55nM has been established for contacting 110nM P+ layers. The P+ layer sheet resistance is reduced to less than 3 ohms per square without compromising the reverse leakage currents of the junctions. The reduction in Gummel number for the P+ layer has reduced the emitter efficiency of the junctions and yielded a factor of four increase in latch-up resistance.
Keywords :
Bipolar transistors; Boron; Contact resistance; Electric resistance; Latches; Leakage current; Schottky diodes; Silicides; Titanium; Windows;
Conference_Titel :
Solid State Device Research Conference, 1987. ESSDERC '87. 17th European
Conference_Location :
Bologna, Italy
