DocumentCode
514112
Title
Three Dimensional Distribution of Latch-Up Current in Scaled CMOS Structures
Author
Selmi, Luca ; Venturi, Franco ; Sangiorgi, Enrico ; Ricco, Bruno
Author_Institution
Department of Electronics, University of Bologna, Viale Risorgimento 2, 40136 Bologna, Italy
fYear
1987
fDate
14-17 Sept. 1987
Firstpage
783
Lastpage
786
Abstract
This paper presents a novel hysteresis phenomenon induced in the latch-up I-V characteristic of CMOS structures by three dimensional effects producing strongly bias dependent non-uniformities in the current lateral distribution. This behavior has been experimentally reproduced in a lumped element circuit, and a suitable model is presented.
Keywords
CMOS technology; Circuit testing; Current density; Current measurement; Electric breakdown; Hysteresis; Low voltage; Proximity effect; Semiconductor device modeling; Thyristors;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1987. ESSDERC '87. 17th European
Conference_Location
Bologna, Italy
Print_ISBN
0444704779
Type
conf
Filename
5436761
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