Design and implementation of a 2.62 uW low-power baseband processor for Passive UHF RFID Tags

In this paper, an ultra-low-power baseband processor for a UHF Passive RFID Tag is presented. It proposes a prominent RFID tag baseband architecture which is compliant with the ISO18000-6B UHF RFID protocol. Several low-power design approaches are employed to reduce the power consumption, including low voltage low operation frequency approach, clock gating technique, clock strobe design, asynchronous operating scheme and optimal power management. The chip has been designed and fabricated successfully in TSMC 0.18 um CMOS Mixed Signal Process. Power analysis shows that the baseband processor consumes 2.62 uW at 1 V supply voltage when it is inventoried by the reader.