Variation-Aware Figure of Merit for Integrated Circuit in Near-Threshold Region

A figure of merit (FOM) for a CMOS system on chip (SoC) is proposed to correctly assess different CMOS SoCs in the near-threshold voltage (V_th) region, where the supply voltage (V_DD) is slightly higher than V_th. When V_DD is scaled down to near V_th, the drain current becomes greatly sensitive to V_DD or V_th; furthermore, the energy exhibits the same sensitivity as that in the super-V_th region. The conventional FOM, the energy-delay product (EDP), is not applicable in the near-V_th region, because the EDP does not consider the sensitivity difference between the energy and the delay. The procedure for establishing an FOM that can appropriately consider the sensitivity difference by fitting the characteristics of a transistor is first introduced. Then, the FOM developed by the proposed procedure is applied to the examples of an inverter chain operating in both the super-V_th and near-V_th regions, which verifies that the proposed FOM is appropriate in the near-V_th region, whereas the EDP is not.