Title :
Area-efficient 100G+ EFEC calculation with Xilinx FPGAs
Author :
Baxter, Michael ; Brebner, Gordon
Author_Institution :
Xilinx Res. Labs., San Jose, CA, USA
Abstract :
This paper presents area-optimized implementations of Galois Field multipliers that exploit the unique programmable logic cells in the Xilinx FPGA, enabling a 100 Gb/s EFEC block with significantly lower footprint within an optical transport FPGA.
Keywords :
Galois fields; field programmable gate arrays; EFEC calculation; Galois field multipliers; Xilinx FPGA; area-optimized implementations; optical transport FPGA; programmable logic cells; Field programmable gate arrays; Forward error correction; Frequency; Optical attenuators; Optical fiber communication; Optical mixing; Optical network units; Programmable logic arrays; Programmable logic devices; Repeaters;
Conference_Titel :
Optical Fiber Communication (OFC), collocated National Fiber Optic Engineers Conference, 2010 Conference on (OFC/NFOEC)
Conference_Location :
San Diego, CA
Electronic_ISBN :
978-1-55752-884-1
