Avalanche Double Photodiode in 40-nm Standard CMOS Technology

This paper investigates a silicon (Si) avalanche double photodiode (ADPD) fabricated in 40-nm standard CMOS technology. Two different types of double photodiodes (DPDs) will be introduced. The first one is a P-well/deep-N-well/P-substrate(PW/DNW/P-substrate) DPD, and the second one is a P+/N-well/P-substrate (P+/NW/P-substrate) DPD. The basic structure of the proposed ADPD is formed by P+/NW and NW/P-substrate junctions in which the avalanche effect occurs at the P+/NW junction. The P+/NW/P-substrate ADPD demonstrates responsivity of 0.84 A/W and a 3-dB electrical bandwidth of 0.7 GHz at 850 nm. For 660 nm, the ADPD shows a responsivity of 0.49 A/W with an electrical bandwidth of 1.8 GHz. For 520 nm, a responsivity of 2.04 A/W and an electrical bandwidth of 1.4 GHz are achieved.