DocumentCode
516152
Title
Implementation of a learning Kohonen neuron based on a pulse stream arithmetics
Author
Hochet, B. ; Peiris, V. ; Abdo, S. ; Declercq, M.
Author_Institution
Electron. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland
Volume
1
fYear
1990
fDate
19-21 Sept. 1990
Firstpage
241
Lastpage
244
Abstract
This paper describes a compact implementation of a three synapse Kohonen neuron with learning capability, using a standard CMOS technology. The synaptic weights are stored on a capacitor as a discrete voltage, input signals are frequency coded pulse streams and special pulse stream arithmetic is used to perform synaptic multiplication and learning.
Keywords
CMOS memory circuits; capacitors; content-addressable storage; learning (artificial intelligence); self-organising feature maps; capacitor; compact implementation; discrete voltage; frequency coded pulse streams; input signals; learning Kohonen neuron; learning capability; pulse stream arithmetics; special pulse stream arithmetic; standard CMOS technology; synaptic multiplication; synaptic weights; three synapse Kohonen neuron; Arithmetic; Biological neural networks; CMOS technology; Capacitors; Clocks; Delay; Hydrogen; Neurons; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1990. ESSCIRC '90. Sixteenth European
Conference_Location
Grenoble
Print_ISBN
2-86332-087-4
Type
conf
Filename
5467724
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