DocumentCode
516177
Title
A 55nsec 4Mb CMOS EPROM
Author
Dallabora, M. ; Rolandi, P. ; Villa, C. ; Maccalli, M.
Author_Institution
SGS-THOMSON Microelectron., Agrate Brianza, Italy
Volume
1
fYear
1990
fDate
19-21 Sept. 1990
Firstpage
161
Lastpage
164
Abstract
A 55 nsec 4Mbit CMOS EPROM has been developed. Fast access time has been achieved splitting bit lines and using mid-word line repeaters. A new matrix biasing scheme is used to improve the Vcc operating range; The device features a typical programming time of 10 usee and an active current of 30 mA; it is produced with a 0.8 um CMOS twin-well process.
Keywords
CMOS memory circuits; EPROM; matrix algebra; repeaters; CMOS EPROM; CMOS twin-well process; current 30 mA; matrix biasing scheme; mid-word line repeaters; size 0.8 mum; splitting bit lines; time 10 mus; time 55 ns; CMOS process; CMOS technology; Capacitance; Decoding; Delay; EPROM; MOS devices; Matrix converters; Redundancy; Repeaters;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1990. ESSCIRC '90. Sixteenth European
Conference_Location
Grenoble
Print_ISBN
2-86332-087-4
Type
conf
Filename
5467758
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