Title :
A Pipelined 330 MHz Multiplier
Author :
Schmitt-Landsiedel, D. ; Noll, T.G. ; Klar, H. ; Enders, G.
Abstract :
An 8 × 8 bit NMOS multiplier test chip for image processing systems has been realized on the basis of a newly designed carry save adder cell, a multiplication rate of 3.3 108 1/sec (fc = 330 MHz) being achieved.
Keywords :
Clocks; Delay; Frequency; Image processing; MOS devices; Pipeline processing; Power dissipation; Registers; Throughput; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference, 1985. ESSCIRC '85. 11th European
Conference_Location :
Toulouse, France
