Title :
A 1.5 Ms/s 8-Bit Pipelined RSD A/D Converter
Author :
Ginetti, B. ; Jespers, P.G.A.
Author_Institution :
Lab. de Microelecronique, Univ. Catholique de Louvain, Louvain-la-Neuve, Belgium
Abstract :
An untrimmed pipelined 8-bits A/D converter with both integral and differential nonlinearity error less than lLsb is presented. At clock frequency of 3 Mhz, the circuit achieves a 1.5 Msample/s data rate. Power consumption is 20 mW and chip area is 2 mm2 in a 3 μm CMOS technology.
Keywords :
CMOS integrated circuits; analogue-digital conversion; CMOS technology; clock frequency; differential nonlinearity error; frequency 3 MHz; integral nonlinearity error; power 20 mW; power consumption; redundant signed digit cyclic converter; size 3 mum; untrimmed pipelined RSD A/D converter; word length 8 bit; CMOS technology; Charge transfer; Circuits; Clocks; Computer architecture; Energy consumption; MOS capacitors; Sampling methods; Signal restoration; Switches;
Conference_Titel :
Solid-State Circuits Conference, 1990. ESSCIRC '90. Sixteenth European
Conference_Location :
Grenoble
Print_ISBN :
2-86332-087-4
