Novel Fault-Tolerant Integrated Mass Storage System

Author

Haraszti, T.P. ; Mento, R.P. ; Moyer, N.A. ; Grant, W.N.

Author_Institution

Microcirc Assoc., Newport Beach, CA, USA

Volume

1

fYear

1990

fDate

19-21 Sept. 1990

Firstpage

141

Lastpage

144

Abstract

Innovative orthogonal shuffle circuits, error correction by weighted codes, associative repair, configurable modular architecture and hierarchical organization are pro- posed for integration of complete mass storage systems on monolithic silicon substrates. Tests on experimental 40-Mbit and 10-Mbit monolithic CMOS static memories demonstrated read and write data rate of 120 MHz, module access time of 25 nsec, power dissipation of 880 mW, mean time between failures of >;0.5 Mhours, data retention time of 10 years, and radiation hardness of 1 Mrad. The experimental memory devices are manufacturable with low cost VLSI processing technologies which are normally used for digital logic circuits only.

Keywords

CMOS memory circuits; VLSI; content-addressable storage; error correction; fault tolerance; integrated circuit testing; radiation hardening (electronics); associative repair; configurable modular architecture; data retention time; error correction; fault-tolerant integrated mass storage system; hierarchical organization; low cost VLSI processing technology; mean time between failures; module access time; monolithic CMOS static memories; monolithic silicon substrates; orthogonal shuffle circuits; power dissipation; radiation hardness; read and write data rate; Circuit testing; Costs; Error correction codes; Fault tolerant systems; Logic circuits; Manufacturing processes; Power dissipation; Read-write memory; Silicon; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1990. ESSCIRC '90. Sixteenth European

Conference_Location

Grenoble

Print_ISBN

2-86332-087-4

Type

conf

Filename

5467766