Title :
Clock Distribution in High Speed A/D Converters
Author :
Barbu, S. ; Le Pailleur, L. ; Giry, L. ; Boutet, M.
Author_Institution :
PHILIPS COMPOSANTS, Caen, France
Abstract :
This paper describes a clock interface suitable in the high speed monolithic bipolar A/D converters. It is based on two main cells. An input buffer drives in a fully symmetrical manner capacitive loads with an optimal slew rate. Then, an adjustable delay circuit gives flexibility in the delay matching around the circuit. This interface implemented in a 7 Ghz bipolar process drives capacitive loads of 20 to 30 pF for clock frequency over 100MHz with 40mW power consumption.
Keywords :
clock distribution networks; convertors; power consumption; adjustable delay circuit; bipolar process; capacitive loads; clock distribution; clock frequency; clock interface; delay matching; flexibility; high speed A/D converters; high speed monolithic bipolar A/D converters; optimal slew rate; power consumption; Clocks; Coupling circuits; Delay; Energy consumption; Flexible printed circuits; Frequency; Pins; Power supplies; Strontium; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1990. ESSCIRC '90. Sixteenth European
Conference_Location :
Grenoble
Print_ISBN :
2-86332-087-4
