DocumentCode
516201
Title
A 1.4GHz Clock Digital Delay Generator
Author
Killips, R.J. ; Taylor, D.G. ; Barber, W. ; Saul, P.H.
Author_Institution
Allen Clark Res. Centre, Plessey Res. Caswell Ltd., Towcester, UK
Volume
1
fYear
1990
fDate
19-21 Sept. 1990
Firstpage
253
Lastpage
256
Abstract
This paper describes the design and evaluation of a 1.4GHz clock rate monolithic digital delay generator. The application area for the device is in digital radio frequency memories (DRFM).
Keywords
UHF generation; clocks; delay circuits; storage management chips; clock rate monolithic digital delay generator; digital radio frequency memory; frequency 1.4 GHz; Clocks; Counting circuits; Delay effects; Digital communication; Frequency; Latches; Pipelines; Radar applications; Random access memory; Read-write memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1990. ESSCIRC '90. Sixteenth European
Conference_Location
Grenoble
Print_ISBN
2-86332-087-4
Type
conf
Filename
5467782
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