• DocumentCode
    516220
  • Title

    A Design Style for VLSI CMOS

  • Author

    Myers, D.J. ; Ivey, P A

  • Author_Institution
    VLSI Design Strategy Group, British Telecom Research Laboratories.
  • fYear
    1984
  • fDate
    0-0 Sept. 1984
  • Firstpage
    252
  • Lastpage
    255
  • Abstract
    Because CMOS is suitable for realising VLSI systems, British Telecom has investigated a number of approaches to dynamic CMOS design. A test chip has been designed to compare techniques, and a complete chip has been designed using a 4-phase logic scheme, believed to be race free.
  • Keywords
    CMOS logic circuits; CMOS technology; Clocks; Logic design; Logic devices; Logic functions; Logic testing; MOS devices; Variable structure systems; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1984. ESSCIRC '84. Tenth European
  • Conference_Location
    Edinburgh, UK
  • Type

    conf

  • Filename
    5467812
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516220