DocumentCode
516234
Title
A 2 μm CMOS, 10 MHz Microprogrammable Signal Processor Core with On-Chip Multiport Memory Bank
Author
Welten, Frank P. ; van Meerbergen, Jef L. ; Delaruelle, Antoine ; Rinner, Klaus ; Schmid, Josef ; van Wyk, Frans J.
Author_Institution
N. V. PHILIPS Research Labs., P.O. Box 80000, WB417, 5600 JA, Eindhoven-The Netherlands. Phone (31)-40-742294
fYear
1984
fDate
0-0 Sept. 1984
Firstpage
8
Lastpage
11
Abstract
In this paper a 2 micron CMOS, MICROPROGRAMMABLE SIGNAL PROCESSOR CORE (SPC) is described, intended as the number crunching unit in Harvard-type digital signal processors. It contains a 16×16 bit Booth multiplier, a 40-bit accumulator, a 32 bit extractor, a format-adjuster, and a 3-port registerfile. Its projected 100 ns. throughput rate makes it highly suitable for applications like HiFi Audio, Telecom and Speech.
Keywords
CMOS process; Data mining; Digital signal processing; Digital signal processors; Hardware; Registers; Signal processing; Speech; Telecommunications; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1984. ESSCIRC '84. Tenth European
Conference_Location
Edinburgh, UK
Type
conf
Filename
5467827
Link To Document