A Unified Theory for Mixed CMOS / BiCMOS Buffer Optimization

A simple yet realistic gate sizing theory is presented to optimize delay of a cascaded gate buffer. The theory is based on the fact that CMOS / BiCMOS gate delay is linearly dependent on fanout f, that is, the delay can be expressed as Af + B, where A and B are coefficients. The optimum fanout fOPT is shown to be approximated as e+B/1.5A for a gate chain. The theory covers various BiCMOS / CMOS gate types such as NAND´s and NOR´s in a unified framework.