An intelligent shrink path for Analog CMOS circuits

The complex nature of analog design makes it difficult to transform analog circuits from one process to another one without extensive manual tuning. Whereas shrinking of layout data is widely used in the digital domain improving performance and reducing area simultaneously, analog circuits, or analog parts of mixed signal circuits usually are redesigned manually. This paper presents a method, that automatically adapts feature sizes of arbitrary analog circuits from one process to another keeping their performance. A mixed digital analog circuit for ISDN-applications containing 6000 analog components and 80 000 digital transistors has been converted from a 2¿ to a 1¿ p-well CMOS process. All aspects of performance have been maintained perfectly while chip area has been reduced to around 35 per cent of the initial design.